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IS61NLF25636A/IS61NVF25636A IS61NLF51218A/IS61NVF51218A
256K x 36 and 512K x 18 9Mb, FLOW THROUGH 'NO WAIT' STATE BUS SRAM
FEATURES
* 100 percent bus utilization * No wait cycles between Read and Write * Internal self-timed write cycle * Individual Byte Write Control * Single Read/Write control pin * Clock controlled, registered address, data and control * Interleaved or linear burst sequence control using MODE input * Three chip enables for simple depth expansion and address pipelining * Power Down mode * Common data inputs and data outputs * CKE pin to enable clock and suspend operation * JEDEC 100-pin TQFP, 119-ball PBGA, and 165ball PBGA packages * Power supply: NVF: VDD 2.5V ( 5%), VDDQ 2.5V ( 5%) NLF: VDD 3.3V ( 5%), VDDQ 3.3V/2.5V ( 5%) * JTAG Boundary Scan for PBGA packages * Industrial temperature available * Lead-free available
ISSI
AUGUST 2005
(R)
DESCRIPTION
The 9 Meg 'NLF/NVF' product family feature high-speed, low-power synchronous static RAMs designed to provide a burstable, high-performance, 'no wait' state, device for networking and communications applications. They are organized as 256K words by 36 bits and 512K words by 18 bits, fabricated with ISSI's advanced CMOS technology. Incorporating a 'no wait' state feature, wait cycles are eliminated when the bus switches from read to write, or write to read. This device integrates a 2-bit burst counter, high-speed SRAM core, and high-drive capability outputs into a single monolithic circuit. All synchronous inputs pass through registers are controlled by a positive-edge-triggered single clock input. Operations may be suspended and all synchronous inputs ignored when Clock Enable, CKE is HIGH. In this state the internal device will hold their previous values. All Read, Write and Deselect cycles are initiated by the ADV input. When the ADV is HIGH the internal burst counter is incremented. New external addresses can be loaded when ADV is LOW. Write cycles are internally self-timed and are initiated by the rising edge of the clock inputs and when WE is LOW. Separate byte enables allow individual bytes to be written. A burst mode pin (MODE) defines the order of the burst sequence. When tied HIGH, the interleaved burst sequence is selected. When tied LOW, the linear burst sequence is selected.
FAST ACCESS TIME
Symbol tKQ tKC Parameter Clock Access Time Cycle Time Frequency 6.5 6.5 7.5 133 7.5 7.5 8.5 117 Units ns ns MHz
Copyright (c) 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
Rev. B 08/26/05
1
IS61NLF25636A/IS61NVF25636A IS61NLF51218A/IS61NVF51218A
BLOCK DIAGRAM
ISSI
(R)
x 36: A [0:17] or x 18: A [0:18]
ADDRESS REGISTER
A2-A17 or A2-A18
256Kx36; 512Kx18 MEMORY ARRAY
MODE A0-A1
BURST ADDRESS COUNTER
A'0-A'1
K
DATA-IN REGISTER
CLK CKE CE CE2 CE2 ADV WE BWY X OE ZZ
CONTROL LOGIC K
WRITE ADDRESS REGISTER
WRITE ADDRESS REGISTER
K
DATA-IN REGISTER
}
CONTROL REGISTER
CONTROL LOGIC
K
(X= a-d, or a,b)
BUFFER
36 or 18 DQx/DQPx
2
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
Rev. B 08/26/05
IS61NLF25636A/IS61NVF25636A IS61NLF51218A/IS61NVF51218A
ISSI
(R)
Bottom View
165-Ball, 13 mm x 15mm BGA
Bottom View
119-Ball, 14 mm x 22 mm BGA
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
Rev. B 08/26/05
3
IS61NLF25636A/IS61NVF25636A IS61NLF51218A/IS61NVF51218A
PIN CONFIGURATION -- 256K X 36, 165-Ball PBGA (TOP VIEW)
1 A B C D E F G H J K L M N P R NC NC DQPc DQc DQc DQc DQc NC DQd DQd DQd DQd DQPd NC MODE 2 A A NC DQc DQc DQc DQc NC DQd DQd DQd DQd NC NC NC 3 CE CE2 VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A 4 BWc BWd VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A A 5 BWb BWa VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDI TMS 6 CE2 CLK VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC A1* A0* 7 CKE WE VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDO TCK 8 ADV OE VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A A 9 A NC VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A
ISSI
10 A A NC DQb DQb DQb DQb NC DQa DQa DQa DQa NC A A 11 NC NC DQPb DQb DQb DQb DQb ZZ DQa DQa DQa DQa DQPa NC A
(R)
Note: A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
PIN DESCRIPTIONS
Symbol A A0, A1 ADV WE CLK CKE BWx (x=a-d) OE ZZ Pin Name Address Inputs Synchronous Burst Address Inputs Synchronous Burst Address Advance/ Load Synchronous Read/Write Control Input Synchronous Clock Clock Enable Synchronous Byte Write Inputs Output Enable Power Sleep Mode MODE TCK, TDI TDO, TMS VDD NC DQx DQPx VDDQ VSS Burst Sequence Selection JTAG Pins 3.3V/2.5V Power Supply No Connect Data Inputs/Outputs Parity Data I/O Isolated output Power Supply 3.3V/2.5V Ground
CE, CE2, CE2 Synchronous Chip Enable
4
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
Rev. B 08/26/05
IS61NLF25636A/IS61NVF25636A IS61NLF51218A/IS61NVF51218A
119-PIN PBGA PACKAGE CONFIGURATION
1 2 3
ISSI
256K x 36 (TOP VIEW)
4 5 6 7
(R)
A B C D E
F
VDDQ NC NC DQc DQc VDDQ DQc DQc VDDQ DQd DQd VDDQ DQd DQd NC NC VDDQ
A CE2 A DQPc DQc DQc DQc DQc VDD DQd DQd DQd DQd DQPd A NC TMS
A A A VSS VSS VSS BWc VSS NC VSS BWd VSS VSS VSS MODE A TDI
NC ADV VDD NC CE OE A WE VDD CLK NC CKE A1* A0* VDD A TCK
A A A Vss Vss Vss BWb Vss NC Vss BWa Vss Vss Vss NC A TDO
A CE2 A DQPb DQb DQb DQb DQb VDD DQa DQa DQa DQa DQPa A NC NC
VDDQ NC NC DQb DQb VDDQ DQb DQb VDDQ DQa DQa VDDQ DQa DQa NC ZZ VDDQ
G H
J
K
L
M N P R T U
Note: A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
PIN DESCRIPTIONS
Symbol A A0, A1 ADV WE CLK CKE CE CE2 CE2 BWx (x=a-d) Pin Name Address Inputs Synchronous Burst Address Inputs Synchronous Burst Address Advance/ Load Synchronous Read/Write Control Input Synchronous Clock Clock Enable Synchronous Chip Select Synchronous Chip Select Synchronous Chip Select Synchronous Byte Write Inputs OE ZZ MODE TCK, TDO TMS, TDI VDD VSS NC DQa-DQd DQPa-Pd VDDQ Output Enable Power Sleep Mode Burst Sequence Selection JTAG Pins Power Supply Ground No Connect Data Inputs/Outputs Parity Data I/O Output Power Supply
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
Rev. B 08/26/05
5
IS61NLF25636A/IS61NVF25636A IS61NLF51218A/IS61NVF51218A
165-PIN PBGA PACKAGE CONFIGURATION
1 2 3 4 5
ISSI
512K x 18 (TOP VIEW)
6 7 8 9 10 11
(R)
A B C D E
F
NC NC NC NC NC NC NC NC DQb DQb DQb DQb DQPb NC MODE
A A NC DQb DQb DQb DQb
CE CE2 VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A
BWb NC Vss VDD VDD VDD VDD VDD VDD VDD VDD VDD Vss A A
NC BWa Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss NC TDI TMS
CE2 CLK Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss NC A1* A0*
CKE WE Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss NC TDO TCK
ADV OE Vss VDD VDD VDD VDD VDD VDD VDD VDD VDD Vss A A
A NC VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A
A A NC NC NC NC NC NC DQa DQa DQa DQa NC A A
A NC DQPa DQa DQa DQa DQa ZZ NC NC NC NC NC NC A
G H
J
NC
NC NC NC NC NC NC NC
K
L
M N P R
Note: A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
PIN DESCRIPTIONS
Symbol A A0, A1 ADV WE CLK CKE BWx (x=a,b) OE ZZ Pin Name Address Inputs Synchronous Burst Address Inputs Synchronous Burst Address Advance/ Load Synchronous Read/Write Control Input Synchronous Clock Clock Enable Synchronous Byte Write Inputs Output Enable Power Sleep Mode MODE TCK, TDI TDO, TMS VDD NC DQx DQPx VDDQ VSS Burst Sequence Selection JTAG Pins 3.3V/2.5V Power Supply No Connect Data Inputs/Outputs Parity Data I/O Isolated output Power Supply 3.3V/2.5V Ground
CE, CE2, CE2 Synchronous Chip Enable
6
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
Rev. B 08/26/05
IS61NLF25636A/IS61NVF25636A IS61NLF51218A/IS61NVF51218A
119-PIN PBGA PACKAGE CONFIGURATION
1 2 3
ISSI
512K x 18 (TOP VIEW)
4 5 6 7
(R)
A B C D E
F
VDDQ NC NC DQb NC VDDQ NC DQb VDDQ NC DQb VDDQ DQb NC NC NC VDDQ
A CE2 A NC DQb NC DQb NC VDD DQb NC DQb NC DQPb A A TMS
A A A VSS VSS VSS BWb VSS NC VSS NC VSS VSS VSS MODE A TDI
NC ADV VDD NC CE OE A WE VDD CLK NC CKE A1* A0* VDD NC TCK
A A A Vss Vss Vss NC Vss NC Vss BWa Vss Vss Vss NC A TDO
A CE2 A DQPa NC DQa NC DQa VDD NC DQa NC DQa NC A A NC
VDDQ NC NC NC DQa VDDQ DQa NC VDDQ DQa NC VDDQ NC DQa NC ZZ VDDQ
G H
J
K
L
M N P R T U
Note: A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
PIN DESCRIPTIONS
Symbol A A0, A1 ADV WE CLK CKE CE CE2 CE2 BWx (x=a,b) Pin Name Address Inputs Synchronous Burst Address Inputs Synchronous Burst Address Advance/ Load Synchronous Read/Write Control Input Synchronous Clock Clock Enable Synchronous Chip Select Synchronous Chip Select Synchronous Chip Select Synchronous Byte Write Inputs OE ZZ MODE TCK, TDO TMS, TDI VDD VSS NC DQa-DQb DQPa-Pb VDDQ Output Enable Power Sleep Mode Burst Sequence Selection JTAG Pins Power Supply Ground No Connect Data Inputs/Outputs Parity Data I/O Output Power Supply
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
Rev. B 08/26/05
7
IS61NLF25636A/IS61NVF25636A IS61NLF51218A/IS61NVF51218A
PIN CONFIGURATION
100-Pin TQFP
ISSI
NC BWb BWa CKE ADV NC CE2 CE2 VDD Vss CLK WE OE NC CE A A A A A
(R)
BWd
BWc BWb
BWa
CKE
OE ADV NC
CLK WE
CE2
CE2 VDD Vss
CE
A
A
A
DQPc DQc DQc VDDQ Vss DQc DQc DQc DQc Vss VDDQ DQc DQc NC VDD NC Vss DQd DQd VDDQ Vss DQd DQd DQd DQd Vss VDDQ DQd DQd DQPd
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 1 79 2 78 3 77 4 76 5 75 6 74 7 73 8 72 9 71 10 70 11 69 12 68 13 67 14 66 15 65 16 64 17 63 18 62 19 61 20 60 21 59 22 58 23 57 24 56 25 55 26 54 27 53 28 52 29 51 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A1 A0 MODE NC NC A A A A Vss VDD NC NC A A A A A A A
A A
DQPb DQb DQb VDDQ Vss DQb DQb DQb DQb Vss VDDQ DQb DQb Vss NC VDD ZZ DQa DQa VDDQ Vss DQa DQa DQa DQa Vss VDDQ DQa DQa DQPa
NC NC NC VDDQ Vss NC NC DQb DQb Vss VDDQ DQb DQb NC VDD NC Vss DQb DQb VDDQ Vss DQb DQb DQPb NC Vss VDDQ NC NC NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 1 79 2 78 3 77 4 76 5 75 6 74 7 73 8 72 9 71 10 70 11 69 12 68 13 67 14 66 15 65 16 64 17 63 18 62 19 61 20 60 21 59 22 58 23 57 24 56 25 55 26 54 27 53 28 52 29 51 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
NC MODE NC A A A A A Vss VDD A1 A0 NC NC A A A A A A
A NC NC VDDQ Vss NC DQPa DQa DQa Vss VDDQ DQa DQa Vss NC VDD ZZ DQa DQa VDDQ Vss DQa DQa NC NC Vss VDDQ NC NC NC
256K x 36
PIN DESCRIPTIONS
A0, A1 Synchronous Address Inputs. These pins must tied to the two LSBs of the address bus. Synchronous Address Inputs Synchronous Clock Synchronous Burst Address Advance Synchronous Byte Write Enable Write Enable Clock Enable Ground for Core Not Connected
512K x 18
CE, CE2, CE2 Synchronous Chip Enable OE DQa-DQd DQPa-DQPd MODE VDD VSS VDDQ ZZ Output Enable Synchronous Data Input/Output Parity Data I/O Burst Sequence Selection +3.3V/2.5V Power Supply Ground for output Buffer Isolated Output Buffer Supply: +3.3V/2.5V Snooze Enable
A CLK ADV BWa-BWd WE CKE Vss NC
8
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
Rev. B 08/26/05
IS61NLF25636A/IS61NVF25636A IS61NLF51218A/IS61NVF51218A
STATE DIAGRAM
READ BEGIN READ WRITE DS READ DS WRITE BEGIN WRITE
ISSI
WRITE
(R)
READ
READ
BURST DS
DESELECT BURST
BURST
WRITE
DS BURST READ WRITE
DS BURST WRITE
BURST
BURST
READ
SYNCHRONOUS TRUTH TABLE(1)
Operation Not Selected Not Selected Not Selected Not Selected Continue Begin Burst Read Continue Burst Read NOP/Dummy Read Dummy Read Begin Burst Write Continue Burst Write NOP/Write Abort Write Abort Ignore Clock Notes:
1. 2. 3. 4.
Address Used N/A N/A N/A N/A External Address Next Address External Address Next Address External Address Next Address N/A Next Address Current Address
CE H X X X L X L X L X L X X
CE2 X L X X H X H X H X H X X
CE2 CE X X H X L X L X L X L X X
ADV L L L H L H L H L H L H X
WE X X X X H X H X L X L X X
BWx BW X X X X X X X X L L H H X
OE X X X X L L H H X X X X X
CKE L L L L L L L L L L L L H
CLK

"X" means don't care. The rising edge of clock is symbolized by A continue deselect cycle can only be entered if a deselect cycle is executed first. WE = L means Write operation in Write Truth Table. WE = H means Read operation in Write Truth Table. 5. Operation finally depends on status of asynchronous pins (ZZ and OE).
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
Rev. B 08/26/05
9
IS61NLF25636A/IS61NVF25636A IS61NLF51218A/IS61NVF51218A
ASYNCHRONOUS TRUTH TABLE(1)
Operation Sleep Mode Read Write Deselected Notes: ZZ H L L L L OE X L H X X I/O STATUS High-Z DQ High-Z Din, High-Z High-Z
ISSI
(R)
1. X means "Don't Care". 2. For write cycles following read cycles, the output buffers must be disabled with OE, otherwise data bus contention will occur. 3. Sleep Mode means power Sleep Mode where stand-by current does not depend on cycle time. 4. Deselected means power Sleep Mode where stand-by current depends on cycle time.
WRITE TRUTH TABLE (x18)
Operation READ WRITE BYTE a WRITE BYTE b WRITE ALL BYTEs WRITE ABORT/NOP Notes: WE H L L L L BWa BW X L H L H BWb BW X H L L H
1. X means "Don't Care". 2. All inputs in this table must beet setup and hold time around the rising edge of CLK.
10
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IS61NLF25636A/IS61NVF25636A IS61NLF51218A/IS61NVF51218A
WRITE TRUTH TABLE (x36)
Operation READ WRITE BYTE a WRITE BYTE b WRITE BYTE c WRITE BYTE d WRITE ALL BYTEs WRITE ABORT/NOP Notes: WE H L L L L L L BWa BW X L H H H L H BWb BW X H L H H L H BWc BW X H H L H L H BWd BW X H H H L L H
ISSI
(R)
1. X means "Don't Care". 2. All inputs in this table must beet setup and hold time around the rising edge of CLK.
INTERLEAVED BURST ADDRESS TABLE (MODE = VDD or NC)
External Address A1 A0 00 01 10 11 1st Burst Address A1 A0 01 00 11 10 2nd Burst Address A1 A0 10 11 00 01 3rd Burst Address A1 A0 11 10 01 00
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Rev. B 08/26/05
11
IS61NLF25636A/IS61NVF25636A IS61NLF51218A/IS61NVF51218A
LINEAR BURST ADDRESS TABLE (MODE = VSS)
ISSI
(R)
0,0
A1', A0' = 1,1
0,1
1,0
ABSOLUTE MAXIMUM RATINGS(1)
Symbol TSTG PD IOUT VIN, VOUT VIN Parameter Storage Temperature Power Dissipation Output Current (per I/O) Voltage Relative to VSS for I/O Pins Voltage Relative to VSS for for Address and Control Inputs Value -65 to +150 1.6 100 -0.5 to VDDQ + 0.3 -0.3 to 4.6 Unit C W mA V V
Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. This device contains circuity to protect the inputs against damage due to high static voltages or electric fields; however, precautions may be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit. 3. This device contains circuitry that will ensure the output devices are in High-Z at power up.
OPERATING RANGE (IS61NLFx)
Range Commercial Industrial Ambient Temperature 0C to +70C -40C to +85C VDD 3.3V 5% 3.3V 5% VDDQ 3.3V / 2.5V 5% 3.3V / 2.5V 5%
12
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Rev. B 08/26/05
IS61NLF25636A/IS61NVF25636A IS61NLF51218A/IS61NVF51218A
OPERATING RANGE (IS61NVFx)
Range Commercial Industrial Ambient Temperature 0C to +70C -40C to +85C VDD 2.5V 5% 2.5V 5% VDDQ 2.5V 5% 2.5V 5%
ISSI
(R)
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
3.3V Symbol VOH VOL VIH VIL ILI ILO Parameter Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Current Output Leakage Current VSS VIN VDD
(1)
2.5V Max. -- 0.4 Min. 2.0 -- 1.7 -0.3 -5 -5 Max. -- 0.4 VDD + 0.3 0.7 5 5 Unit V V V V A A
Test Conditions IOH = -4.0 mA (3.3V) IOH = -1.0 mA (2.5V) IOL = 8.0 mA (3.3V) IOL = 1.0 mA (2.5V)
Min. 2.4 -- 2.0 -0.3 -5 -5
VDD + 0.3 0.8 5 5
VSS VOUT VDDQ, OE = VIH
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
6.5 MAX x18 x36 280 300 280 300 7.5 MAX x18 x36 270 280 270 280
Symbol Parameter ICC AC Operating Supply Current
Test Conditions
Temp. range
Unit mA
Device Selected, Com. OE = VIH, ZZ VIL, Ind. All Inputs 0.2V or VDD - 0.2V, Cycle Time tKC min. Device Deselected, VDD = Max., All Inputs VIL or VIH, ZZ VIL, f = Max. Com. Ind.
ISB
Standby Current TTL Input
100 100
100 100
100 100
100 100
mA
ISBI
Standby Current CMOS Input
Device Deselected, Com. VDD = Max., Ind. VIN VSS + 0.2V or VDD - 0.2V f=0 ZZ > VIH Com. Ind.
70 80
70 80
70 80
70 80
mA
ISB2
Sleep Mode
45 50
45 50
45 50
45 50
mA
Note: 1. MODE pin has an internal pullup and should be tied to VDD or VSS. It exhibits 100 A maximum leakage current when tied to VSS + 0.2V or VDD - 0.2V.
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Rev. B 08/26/05
13
IS61NLF25636A/IS61NVF25636A IS61NLF51218A/IS61NVF51218A
CAPACITANCE(1,2)
Symbol CIN COUT Parameter Input Capacitance Input/Output Capacitance Conditions VIN = 0V VOUT = 0V Max. 6 8 Unit pF pF
ISSI
(R)
Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: TA = 25C, f = 1 MHz, VDD = 3.3V.
3.3V I/O AC TEST CONDITIONS
Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load Unit 0V to 3.0V 1.5 ns 1.5V See Figures 1 and 2
3.3V I/O OUTPUT LOAD EQUIVALENT
317
Zo= 50
OUTPUT
+3.3V
OUTPUT
50
1.5V
351
5 pF Including jig and scope
Figure 1
Figure 2
14
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
Rev. B 08/26/05
IS61NLF25636A/IS61NVF25636A IS61NLF51218A/IS61NVF51218A
2.5V I/O AC TEST CONDITIONS
Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load Unit 0V to 2.5V 1.5 ns 1.25V See Figures 3 and 4
ISSI
(R)
2.5V I/O OUTPUT LOAD EQUIVALENT
1,667
ZO = 50 OUTPUT
+2.5V
OUTPUT
50
1,538
1.25V
5 pF Including jig and scope
Figure 3
Figure 4
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
Rev. B 08/26/05
15
IS61NLF25636A/IS61NVF25636A IS61NLF51218A/IS61NVF51218A
READ/WRITE CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
Symbol fmax tKC tKH tKL tKQ tKQX
(2) (2,3)
ISSI
6.5 Min. Max. -- 7.5 2.2 2.2 -- 2.5 2.5 -- -- 0 -- 1.5 1.5 1.5 1.5 1.5 1.5 0.5 0.5 0.5 0.5 0.5 0.5 -- -- 133 -- -- -- 6.5 -- -- 3.8 3.2 -- 3.5 -- -- -- -- -- -- -- -- -- -- -- -- 2 2 7.5 Min. Max. -- 8.5 2.5 2.5 -- 2.5 2.5 -- -- 0 -- 1.5 1.5 1.5 1.5 1.5 1.5 0.5 0.5 0.5 0.5 0.5 0.5 -- -- 117 -- -- -- 7.5 -- -- 4.0 3.4 -- 3.5 -- -- -- -- -- -- -- -- -- -- -- -- 2 2 Unit MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns cyc cyc
(R)
Parameter Clock Frequency Cycle Time Clock High Time Clock Low Time Clock Access Time Clock High to Output Invalid Clock High to Output Low-Z Clock High to Output High-Z Output Enable to Output Valid Output Enable to Output Low-Z Output Disable to Output High-Z Address Setup Time Read/Write Setup Time Chip Enable Setup Time Clock Enable Setup Time Address Advance Setup Time Data Setup Time Address Hold Time Clock Enable Hold Time Write Hold Time Chip Enable Hold Time Address Advance Hold Time Data Hold Time ZZ High to Power Down ZZ Low to Power Down
tKQLZ tOEQ tOELZ tAS tWS tCES tSE
tKQHZ(2,3)
(2,3) (2,3)
tOEHZ
tADVS tDS tAH tHE tWH tCEH tADVH tDH tPDS tPUS Notes:
1. Configuration signal MODE is static and must not change during normal operation. 2. Guaranteed but not 100% tested. This parameter is periodically sampled. 3. Tested with load in Figure 2.
16
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Rev. B 08/26/05
IS61NLF25636A/IS61NVF25636A IS61NLF51218A/IS61NVF51218A
SLEEP MODE ELECTRICAL CHARACTERISTICS
Symbol ISB2 tPDS tPUS tZZI tRZZI Parameter Current during SLEEP MODE ZZ active to input ignored ZZ inactive to input sampled ZZ active to SLEEP current ZZ inactive to exit SLEEP current 2 2 0 Conditions ZZ VIH Min. Max. 60 2
ISSI
Unit mA cycle cycle cycle ns
(R)
SLEEP MODE TIMING
CLK
tPDS ZZ setup cycle tPUS ZZ recovery cycle
ZZ
tZZI
Isupply
ISB2 tRZZI
All Inputs (except ZZ)
Deselect or Read Only
Deselect or Read Only Normal operation cycle
Outputs (Q)
High-Z Don't Care
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Rev. B 08/26/05
17
IS61NLF25636A/IS61NVF25636A IS61NLF51218A/IS61NVF51218A
READ CYCLE TIMING
ISSI
(R)
tKH tKL
CLK
tADVS tADVH
ADV
tKC
tAS tAH
Address A1 A2 A3
tWS tWH
WRITE
tSE tHE
CKE
tCES tCEH
CE
OE
tOEQ tOEHZ
Data Out
Q1-1
tOEHZ
tDS
Q2-1
tKQ tKQHZ
Q2-2 Q2-3 Q2-4 Q3-1 Q3-2 Q3-3 Q3-4
NOTES: WRITE = L means WE = L and BWx = L WE = L and BWX = L CE = L means CE1 = L, CE2 = H and CE2 = L CE = H means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = L
Don't Care Undefined
18
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Rev. B 08/26/05
IS61NLF25636A/IS61NVF25636A IS61NLF51218A/IS61NVF51218A
WRITE CYCLE TIMING
tKH tKL
CLK
ISSI
(R)
tKC
ADV
Address
A1
A2
A3
WRITE
tSE tHE
CKE
CE
OE
tDS
Data In
D1-1 D2-1 D2-2 D2-3 D2-4 D3-1 D3-2
tDH
D3-3 D3-4
tOEHZ
Data Out
Q0-4
NOTES: WRITE = L means WE = L and BWx = L WE = L and BWX = L CE = L means CE1 = L, CE2 = H and CE2 = L CE = H means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = L
Don't Care Undefined
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19
IS61NLF25636A/IS61NVF25636A IS61NLF51218A/IS61NVF51218A
SINGLE READ/WRITE CYCLE TIMING
tKH tKL
ISSI
(R)
CLK
tSE tHE tKC
CKE
Address
A1
A2
A3
A4
A5
A6
A7
A8
A9
WRITE
CE
ADV
OE
tOEQ tOELZ
Data Out
Q1
tDS tDH
Q3
Q4
Q6
Q7
Data In
D2
NOTES: WRITE = L means WE = L and BWx = L CE = L means CE1 = L, CE2 = H and CE2 = L CE = H means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = L
D5
Don't Care Undefined
20
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IS61NLF25636A/IS61NVF25636A IS61NLF51218A/IS61NVF51218A
CKE OPERATION TIMING
tKH tKL
ISSI
(R)
CLK
tSE tHE tKC
CKE
Address
A1
A2
A3
A4
A5
A6
WRITE
CE
ADV
OE
tKQ tKQLZ tKQHZ
Data Out
Q1
tDS tDH
Q3
Q4
Data In
D2
NOTES: WRITE = L means WE = L and BWx = L CE = L means CE1 = L, CE2 = H and CE2 = L CE = H means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = L
D5
Don't Care Undefined
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21
IS61NLF25636A/IS61NVF25636A IS61NLF51218A/IS61NVF51218A
CE OPERATION TIMING
tKH tKL
ISSI
tKC
(R)
CLK
tSE tHE
CKE
Address
A1
A2
A3
A4
A5
WRITE
CE
ADV
OE
tOEQ tOELZ tKQHZ tKQ tKQLZ
Data Out
Q1
Q2
tDS tDH
Q4
Data In
D3
NOTES: WRITE = L means WE = L and BWx = L CE = L means CE1 = L, CE2 = H and CE2 = L CE = H means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = L
D5
Don't Care Undefined
22
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Rev. B 08/26/05
IS61NLF25636A/IS61NVF25636A IS61NLF51218A/IS61NVF51218A
IEEE 1149.1 SERIAL BOUNDARY SCAN (JTAG)
The IS61NLFX and IS61NVFX have a serial boundary scan Test Access Port (TAP) in the PBGA package only. (Not available in TQFP package.) This port operates in accordance with IEEE Standard 1149.1-1900, but does not include all functions required for full 1149.1 compliance. These functions from the IEEE specification are excluded because they place added delay in the critical speed path of the SRAM. The TAP controller operates in a manner that does not conflict with the performance of other devices using 1149.1 fully compliant TAPs. The TAP operates using JEDEC standard 2.5V I/O logic levels.
ISSI
TEST MODE SELECT (TMS)
(R)
TEST ACCESS PORT (TAP) - TEST CLOCK
The test clock is only used with the TAP controller. All inputs are captured on the rising edge of TCK and outputs are driven from the falling edge of TCK.
The TMS input is used to send commands to the TAP controller and is sampled on the rising edge of TCK. This pin may be left disconnected if the TAP is not used. The pin is internally pulled up, resulting in a logic HIGH level.
TEST DATA-IN (TDI)
The TDI pin is used to serially input information to the registers and can be connected to the input of any register. The register between TDI and TDO is chosen by the instruction loaded into the TAP instruction register. For information on instruction register loading, see the TAP Controller State Diagram. TDI is internally pulled up and can be disconnected if the TAP is unused in an application. TDI is connected to the Most Significant Bit (MSB) on any register.
DISABLING THE JTAG FEATURE
The SRAM can operate without using the JTAG feature. To disable the TAP controller, TCK must be tied LOW (VSS) to prevent clocking of the device. TDI and TMS are internally pulled up and may be disconnected. They may alternately be connected to VDD through a pull-up resistor. TDO should be left disconnected. On power-up, the device will start in a reset state which will not interfere with the device operation.
TAP CONTROLLER BLOCK DIAGRAM
0 Bypass Register
2 TDI Selection Circuitry
1
0 Selection Circuitry TDO
Instruction Register
31 30 29
...
2
1
0
Identification Register
x
.....
Boundary Scan Register*
2
1
0
TCK TMS
TAP CONTROLLER
23
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IS61NLF25636A/IS61NVF25636A IS61NLF51218A/IS61NVF51218A
TEST DATA OUT (TDO)
The TDO output pin is used to serially clock data-out from the registers. The output is active depending on the current state of the TAP state machine (see TAP Controller State Diagram). The output changes on the falling edge of TCK and TDO is connected to the Least Significant Bit (LSB) of any register.
ISSI
Boundary Scan Register
(R)
is set LOW (VSS) when the BYPASS instruction is executed. The boundary scan register is connected to all input and output pins on the SRAM. Several no connect (NC) pins are also included in the scan register to reserve pins for higher density devices. The x36 configuration has a 75-bit-long register and the x18 configuration also has a 75-bit-long register. The boundary scan register is loaded with the contents of the RAM Input and Output ring when the TAP controller is in the Capture-DR state and then placed between the TDI and TDO pins when the controller is moved to the Shift-DR state. The EXTEST, SAMPLE/PRELOAD and SAMPLE-Z instructions can be used to capture the contents of the Input and Output ring. The Boundary Scan Order tables show the order in which the bits are connected. Each bit corresponds to one of the bumps on the SRAM package. The MSB of the register is connected to TDI, and the LSB is connected to TDO.
PERFORMING A TAP RESET
A Reset is performed by forcing TMS HIGH (VDD) for five rising edges of TCK. RESET may be performed while the SRAM is operating and does not affect its operation. At power-up, the TAP is internally reset to ensure that TDO comes up in a high-Z state.
TAP REGISTERS
Registers are connected between the TDI and TDO pins and allow data to be scanned into and out of the SRAM test circuitry. Only one register can be selected at a time through the instruction registers. Data is serially loaded into the TDI pin on the rising edge of TCK and output on the TDO pin on the falling edge of TCK.
Instruction Register
Three-bit instructions can be serially loaded into the instruction register. This register is loaded when it is placed between the TDI and TDO pins. (See TAP Controller Block Diagram) At power-up, the instruction register is loaded with the IDCODE instruction. It is also loaded with the IDCODE instruction if the controller is placed in a reset state as previously described. When the TAP controller is in the CaptureIR state, the two least significant bits are loaded with a binary "01" pattern to allow for fault isolation of the board level serial test path.
Scan Register Sizes
Register Name Instruction Bypass ID Boundary Scan Bit Size (x18) 3 1 32 75 Bit Size (x36) 3 1 32 75
Bypass Register
To save time when serially shifting data through registers, it is sometimes advantageous to skip certain states. The bypass register is a single-bit register that can be placed between TDI and TDO pins. This allows data to be shifted through the SRAM with minimal delay. The bypass register
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code during the Capture-DR state when the IDCODE command is loaded to the instruction register. The IDCODE is hardwired into the SRAM and can be shifted out when the TAP controller is in the Shift-DR state. The ID register has vendor code and other information described in the Identification Register Definitions table.
IDENTIFICATION REGISTER DEFINITIONS
Instruction Field Revision Number (31:28) Device Depth (27:23) Device Width (22:18) ISSI Device ID (17:12) ISSI JEDEC ID (11:1) ID Register Presence (0) 24 Description Reserved for version number. Defines depth of SRAM. 256K or 512K Defines Width of the SRAM. x36 or x18 Reserved for future use. Allows unique identification of SRAM vendor. Indicate the presence of an ID register. 256K x 36 xxxx 00111 00100 xxxxx 00011010101 1 512K x 18 xxxx 01000 00011 xxxxx 00011010101 1
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IS61NLF25636A/IS61NVF25636A IS61NLF51218A/IS61NVF51218A
TAP INSTRUCTION SET
Eight instructions are possible with the three-bit instruction register and all combinations are listed in the Instruction Code table. Three instructions are listed as RESERVED and should not be used and the other five instructions are described below. The TAP controller used in this SRAM is not fully compliant with the 1149.1 convention because some mandatory instructions are not fully implemented. The TAP controller cannot be used to load address, data or control signals and cannot preload the Input or Output buffers. The SRAM does not implement the 1149.1 commands EXTEST or INTEST or the PRELOAD portion of SAMPLE/PRELOAD; instead it performs a capture of the Inputs and Output ring when these instructions are executed. Instructions are loaded into the TAP controller during the Shift-IR state when the instruction register is placed between TDI and TDO. During this state, instructions are shifted from the instruction register through the TDI and TDO pins. To execute an instruction once it is shifted in, the TAP controller must be moved into the Update-IR state.
ISSI
SAMPLE/PRELOAD
(R)
EXTEST
EXTEST is a mandatory 1149.1 instruction which is to be executed whenever the instruction register is loaded with all 0s. Because EXTEST is not implemented in the TAP controller, this device is not 1149.1 standard compliant. The TAP controller recognizes an all-0 instruction. When an EXTEST instruction is loaded into the instruction register, the SRAM responds as if a SAMPLE/PRELOAD instruction has been loaded. There is a difference between the instructions, unlike the SAMPLE/PRELOAD instruction, EXTEST places the SRAM outputs in a High-Z state.
IDCODE
The IDCODE instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. It also places the instruction register between the TDI and TDO pins and allows the IDCODE to be shifted out of the device when the TAP controller enters the Shift-DR state. The IDCODE instruction is loaded into the instruction register upon power-up or whenever the TAP controller is given a test logic reset state.
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. The PRELOAD portion of this instruction is not implemented, so the TAP controller is not fully 1149.1 compliant. When the SAMPLE/PRELOAD instruction is loaded to the instruction register and the TAP controller is in the Capture-DR state, a snapshot of data on the inputs and output pins is captured in the boundary scan register. It is important to realize that the TAP controller clock operates at a frequency up to 10 MHz, while the SRAM clock runs more than an order of magnitude faster. Because of the clock frequency differences, it is possible that during the Capture-DR state, an input or output will under-go a transition. The TAP may attempt a signal capture while in transition (metastable state). The device will not be harmed, but there is no guarantee of the value that will be captured or repeatable results. To guarantee that the boundary scan register will capture the correct signal value, the SRAM signal must be stabilized long enough to meet the TAP controller's capture set-up plus hold times (tCS and tCH). To insure that the SRAM clock input is captured correctly, designs need a way to stop (or slow) the clock during a SAMPLE/ PRELOAD instruction. If this is not an issue, it is possible to capture all other signals and simply ignore the value of the CLK captured in the boundary scan register. Once the data is captured, it is possible to shift out the data by putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO pins. Note that since the PRELOAD part of the command is not implemented, putting the TAP into the Update to the Update-DR state while performing a SAMPLE/PRELOAD instruction will have the same effect as the Pause-DR command.
BYPASS
When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between the TDI and TDO pins. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board.
SAMPLE-Z
The SAMPLE-Z instruction causes the boundary scan register to be connected between the TDI and TDO pins when the TAP controller is in a Shift-DR state. It also places all SRAM outputs into a High-Z state.
RESERVED
These instructions are not implemented but are reserved for future use. Do not use these instructions.
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IS61NLF25636A/IS61NVF25636A IS61NLF51218A/IS61NVF51218A
INSTRUCTION CODES
Code 000 Instruction EXTEST Description
ISSI
(R)
Captures the Input/Output ring contents. Places the boundary scan register between the TDI and TDO. Forces all SRAM outputs to High-Z state. This instruction is not 1149.1 compliant. Loads the ID register with the vendor ID code and places the register between TDI and TDO. This operation does not affect SRAM operation. Captures the Input/Output contents. Places the boundary scan register between TDI and TDO. Forces all SRAM output drivers to a High-Z state. Do Not Use: This instruction is reserved for future use. Captures the Input/Output ring contents. Places the boundary scan register between TDI and TDO. Does not affect the SRAM operation. This instruction does not implement 1149.1 preload function and is therefore not 1149.1 compliant. Do Not Use: This instruction is reserved for future use. Do Not Use: This instruction is reserved for future use. Places the bypass register between TDI and TDO. This operation does not affect SRAM operation.
001 010 011 100
IDCODE SAMPLE-Z RESERVED SAMPLE/PRELOAD
101 110 111
RESERVED RESERVED BYPASS
TAP CONTROLLER STATE DIAGRAM
Test Logic Reset 1 0 Run Test/Idle 0 1 1 Select DR 0 Capture DR 0 Shift DR 1 Exit1 DR 0 1 Select IR 0 1 Capture IR 0 Shift IR 1 Exit1 IR 0 Pause IR 1 0 Exit2 IR 1 1
0 1
0 1
Pause DR 0 1 0 1 Exit2 DR 1 Update DR 0
0
1
Update IR 0
26
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IS61NLF25636A/IS61NVF25636A IS61NLF51218A/IS61NVF51218A
TAP Electrical Characteristics Over the Operating Range(1,2)
Symbol VOH1 VOH2 VOL1 VOL2 VIH VIL IX Notes:
1. All Voltage referenced to Ground. 2. Overshoot: VIH (AC) VDD +1.5V for t tTCYC/2, Undershoot: VIL (AC) 0.5V for t tTCYC/2, Power-up: VIH < 2.6V and VDD < 2.4V and VDDQ < 1.4V for t < 200 ms.
ISSI
Test Conditions IOH = -2.0 mA IOH = -100 A IOL = 2.0 mA IOL = 100 A Min. 1.7 2.1 -- -- 1.7 -0.3 VSS V I VDDQ -10 Max. -- -- 0.7 0.2 VDD +0.3 0.7 10 V V V V V V A
(R)
Parameter Output HIGH Voltage Output HIGH Voltage Output LOW Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Current
Units
TAP AC ELECTRICAL CHARACTERISTICS(1,2) (OVER OPERATING RANGE)
Symbol Parameter tTCYC fTF tTH tTL tTMSS tTDIS tCS tTMSH tTDIH tCH tTDOV tTDOX Notes:
1. tCS and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register. 2. Test conditions are specified using the load in TAP AC test conditions. tR/tF = 1 ns.
Min. 100 -- 40 40 10 10 10 10 10 10 -- 0
Max. -- 10 -- -- -- -- -- -- -- -- 20 --
Unit ns MHz ns ns ns ns ns ns ns ns ns ns
TCK Clock cycle time TCK Clock frequency TCK Clock HIGH TCK Clock LOW TMS setup to TCK Clock Rise TDI setup to TCK Clock Rise Capture setup to TCK Rise TMS hold after TCK Clock Rise TDI Hold after Clock Rise Capture hold after Clock Rise TCK LOW to TDO valid TCK LOW to TDO invalid
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IS61NLF25636A/IS61NVF25636A IS61NLF51218A/IS61NVF51218A
TAP AC TEST CONDITIONS (2.5V/3.3V)
Input pulse levels Input rise and fall times Input timing reference levels Output reference levels Test load termination supply voltage Vtrig 0 to 2.5V/0 to 3.0V 1ns 1.25V/1.5V 1.25V/1.5V 1.25V/1.5V 1.25V/1.5V
ISSI
TAP Output Load Equivalent 50 Vtrig
(R)
TDO Z0 = 50 20 pF GND
TAP TIMING
1 tTHTH TCK
2 tTLTH
3
4
5
6
tTHTL tMVTH tTHMX
TMS tDVTH tTHDX TDI tTLOV TDO tTLOX DON'T CARE UNDEFINED
28
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IS61NLF25636A/IS61NVF25636A IS61NLF51218A/IS61NVF51218A
165 PBGA BOUNDARY SCAN ORDER (x 36)
Bit # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Signal Bump Name ID MODE NC NC A A A A A A A ZZ DQa DQa DQa DQa DQa DQa DQa DQa DQa 1R 6N 11P 8P 8R 9R 9P 10P 10R 11R 11H 11N 11M 11L 11K 11J 10M 10L 10K 10J Bit # 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Signal Name DQb DQb DQb DQb DQb DQb DQb DQb DQb NC A A A NC ADV OE CKE WE CLK NC Bump ID 11G 11F 11E 11D 10G 10F 10E 10D 11C 11A 10A 10B 9A 9B 8A 8B 7A 7B 6B 11B Bit # 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 Signal Name NC CE2 BWa BWb BWc BWd CE2 CE A A NC DQc DQc DQc DQc DQc DQc DQc DQc DQc Bump ID 1A 6A 5B 5A 4A 4B 3B 3A 2A 2B 1B 1C 1D 1E 1F 1G 2D 2E 2F 2G Bit # 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75
ISSI
Signal Name DQd DQd DQd DQd DQd DQd DQd DQd DQd A A A A A1 A0 1J 1K 1L 1M 2J 2K 2L 2M 1N 3P 3R 4R 4P 6P 6R
(R)
Bump ID
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IS61NLF25636A/IS61NVF25636A IS61NLF51218A/IS61NVF51218A
165 PBGA BOUNDARY SCAN ORDER (x 18)
Bit # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Signal Bump Name ID MODE NC NC A A A A A A A ZZ NC NC NC NC NC DQa DQa DQa DQa 1R 6N 11P 8P 8R 9R 9P 10P 10R 11R 11H 11N 11M 11L 11K 11J 10M 10L 10K 10J Bit # 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Signal Name DQa DQa DQa DQa DQa NC NC NC NC A A A A NC ADV OE CKE WE CLK NC Bump ID 11G 11F 11E 11D 11C 10F 10E 10D 10G 11A 10A 10B 9A 9B 8A 8B 7A 7B 6B 11B Bit # 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 Signal Name NC CE2 BWa NC BWb NC CE2 CE A A NC NC NC NC NC NC DQb DQb DQb DQb Bump ID 1A 6A 5B 5A 4A 4B 3B 3A 2A 2B 1B 1C 1D 1E 1F 1G 2D 2E 2F 2G Bit # 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75
ISSI
Signal Name DQb DQb DQb DQb DQb NC NC NC NC A A A A A1 A0 1J 1K 1L 1M 1N 2K 2L 2M 2J 3P 3R 4R 4P 6P 6R
(R)
Bump ID
30
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IS61NLF25636A/IS61NVF25636A IS61NLF51218A/IS61NVF51218A
119 BOUNDARY SCAN ORDER (256K X 36)
ISSI
(R)
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IS61NLF25636A/IS61NVF25636A IS61NLF51218A/IS61NVF51218A
119 BOUNDARY SCAN ORDER (512K X 18)
ISSI
(R)
32
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IS61NLF25636A/IS61NVF25636A IS61NLF51218A/IS61NVF51218A
ORDERING INFORMATION (VDD = 3.3V/VDDQ = 2.5V/3.3V) Commercial Range: 0C to +70C
Access Time 6.5 Order Part Number 256Kx36 IS61NLF25636A-6.5TQ IS61NLF25636A-6.5B2 IS61NLF25636A-6.5B3 7.5 IS61NLF25636A-7.5TQ IS61NLF25636A-7.5B2 IS61NLF25636A-7.5B3 512Kx18 6.5 IS61NLF51218A-6.5TQ IS61NLF51218A-6.5B2 IS61NLF51218A-6.5B3 IS61NLF51218A-7.5TQ IS61NLF51218A-7.5B2 IS61NLF51218A-7.5B3 100 TQFP 119 PBGA 165 PBGA 100 TQFP 119 PBGA 165 PBGA 100 TQFP 119 PBGA 165 PBGA 100 TQFP 119 PBGA 165 PBGA Package
ISSI
(R)
7.5
Industrial Range: -40C to +85C
Access Time 6.5 Order Part Number 256Kx36 IS61NLF25636A-6.5TQI IS61NLF25636A-6.5B2I IS61NLF25636A-6.5B3I IS61NLF25636A-7.5TQI IS61NLF25636A-7.5TQLI IS61NLF25636A-7.5B2I IS61NLF25636A-7.5B3I 512Kx18 6.5 IS61NLF51218A-6.5TQI IS61NLF51218A-6.5B2I IS61NLF51218A-6.5B3I IS61NLF51218A-7.5TQI IS61NLF51218A-7.5TQLI IS61NLF51218A-7.5B2I IS61NLF51218A-7.5B3I 100 TQFP 119 PBGA 165 PBGA 100 TQFP 100 TQFP, Lead-free 119 PBGA 165 PBGA 100 TQFP 119 PBGA 165 PBGA 100 TQFP 100 TQFP, Lead-free 119 PBGA 165 PBGA Package
7.5
7.5
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IS61NLF25636A/IS61NVF25636A IS61NLF51218A/IS61NVF51218A
ORDERING INFORMATION (VDD = 2.5V/VDDQ = 2.5V) Commercial Range: 0C to +70C
Access Time 6.5 Order Part Number 256Kx36 IS61NVF25636A-6.5TQ IS61NVF25636A-6.5B2 IS61NVF25636A-6.5B3 IS61NVF25636A-7.5TQ IS61NVF25636A-7.5B2 IS61NVF25636A-7.5B3 512Kx18 6.5 IS61NVF51218A-6.5TQ IS61NVF51218A-6.5B2 IS61NVF51218A-6.5B3 IS61NVF51218A-7.5TQ IS61NVF51218A-7.5B2 IS61NVF51218A-7.5B3 100 TQFP 119 PBGA 165 PBGA 100 TQFP 119 PBGA 165 PBGA 100 TQFP 119 PBGA 165 PBGA 100 TQFP 119 PBGA 165 PBGA Package
ISSI
(R)
7.5
7.5
Industrial Range: -40C to +85C
Access Time 6.5 Order Part Number 256Kx36 IS61NVF25636A-6.5TQI IS61NVF25636A-6.5B2I IS61NVF25636A-6.5B3I IS61NVF25636A-7.5TQI IS61NVF25636A-7.5B2I IS61NVF25636A-7.5B3I 512Kx18 6.5 IS61NVF51218A-6.5TQI IS61NVF51218A-6.5B2I IS61NVF51218A-6.5B3I IS61NVF51218A-7.5TQI IS61NVF51218A-7.5B2I IS61NVF51218A-7.5B3I 100 TQFP 119 PBGA 165 PBGA 100 TQFP 119 PBGA 165 PBGA 100 TQFP 119 PBGA 165 PBGA 100 TQFP 119 PBGA 165 PBGA Package
7.5
7.5
34
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PACKAGING INFORMATION
Plastic Ball Grid Array Package Code: B (119-pin)
ISSI
b (119X)
7 6 5 4 32 1 A B C D E F G H J K L M N P R T U
(R)
E
A
30
D
D2
D1
e
A2 E2 A3 A1
E1
A4
SEATING PLANE
MILLIMETERS Sym.
N0. Leads A A1 A2 A3 A4 b D D1 D2 E E1 E2 e -- 0.50 0.80 1.30 0.60 21.80 19.40 13.80 11.90
INCHES Min. Max.
Notes:
Min.
119
Max.
2.41 0.70 1.00 1.70 0.90 22.20 19.60 14.20 12.10
-- 0.020 0.032 0.051 0.024 0.858 0.764 0.543 0.469
0.095 0.028 0.039 0.067 0.035 0.874 0.772 0.559 0.476
1. Controlling dimension: millimeters, unless otherwise specified. 2. BSC = Basic lead spacing between centers. 3. Dimensions D1 and E do not include mold flash protrusion and should be measured from the bottom of the package. 4. Formed leads shall be planar with respect to one another within 0.004 inches at the seating plane.
0.56 BSC
0.022 BSC
20.32 BSC
0.800 BSC
7.62 BSC 1.27 BSC
0.300 BSC 0.050 BSC
Copyright (c) 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
Rev. B 02/12/03
PACKAGING INFORMATION
Ball Grid Array Package Code: B (165-pin)
TOP VIEW
A1 CORNER 1
A B C D E F G H J K L M N P R
b (165X)
ISSI
BOTTOM VIEW
A1 CORNER 9 8 7 6 5 4 3 2 1
A B C D
(R)
2
3
4
5
6
7
8
9
10
11
11 10
e
E F G
D D1
H J K L M N P R
e E1 E A2 A1 A
BGA - 13mm x 15mm
MILLIMETERS Sym.
N0. Leads A A1 A2 D D1 E E1 e b -- 0.25 -- 14.90 13.90 12.90 9.90 -- 0.40
INCHES Min. Nom. Max.
165
Notes: 1. Controlling dimensions are in millimeters.
Min.
Nom. Max.
165 -- 0.33 0.79 15.00 14.00 13.00 10.00 1.20 0.40 -- 15.10 14.10 13.10 10.10 -- 0.50
-- 0.010 -- 0.587 0.547 0.508 0.390 -- 0.016
-- 0.031 0.591 0.551 0.512 0.394 0.039 0.018
0.047 -- 0.594 0.555 0.516 0.398 -- 0.020
0.013 0.016
1.00
0.45
Copyright (c) 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
Rev. A 06/11/03
PACKAGING INFORMATION
TQFP (Thin Quad Flat Pack Package) Package Code: TQ
ISSI
D D1
(R)
E
E1
N
1
C e SEATING PLANE
L1 L
A2 A1 b
A
Millimeters Symbol Min Max Ref. Std. No. Leads (N) 100 A -- 1.60 -- 0.063 A1 0.05 0.15 0.002 0.006 A2 1.35 1.45 0.053 0.057 b 0.22 0.38 0.009 0.015 D 21.90 22.10 0.862 0.870 D1 19.90 20.10 0.783 0.791 E 15.90 16.10 0.626 0.634 E1 13.90 14.10 0.547 0.555 e 0.65 BSC 0.026 BSC L 0.45 0.75 0.018 0.030 L1 1.00 REF. 0.039 REF. C 0o 7o 0o 7o
Thin Quad Flat Pack (TQ) Inches Millimeters Min Max Min Max 128 -- 1.60 0.05 0.15 1.35 1.45 0.17 0.27 21.80 22.20 19.90 20.10 15.80 16.20 13.90 14.10 0.50 BSC 0.45 0.75 1.00 REF. 0o 7o
Inches Min Max
-- 0.063 0.002 0.006 0.053 0.057 0.007 0.011 0.858 0.874 0.783 0.791 0.622 0.638 0.547 0.555 0.020 BSC 0.018 0.030 0.039 REF. 0o 7o
Notes: 1. All dimensioning and tolerancing conforms to ANSI Y14.5M-1982. 2. Dimensions D1 and E1 do not include mold protrusions. Allowable protrusion is 0.25 mm per side. D1 and E1 do include mold mismatch and are determined at datum plane -H-. 3. Controlling dimension: millimeters.
Integrated Silicon Solution, Inc. -- 1-800-379-4774
PK13197LQ Rev. D 05/08/03

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